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-- Company: 
-- Engineer: 
-- 
-- Create Date:    18:37:02 05/08/2012 
-- Design Name: 
-- Module Name:    TSP_ShiftRegister - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
use work.FAW_TYPES.all;

entity TSP_ShiftRegister is
        Port ( 
                          clk_tspsr : in  STD_LOGIC;
        --                system_clk_rspsr : in STD_LOGIC;
           data_in_tspsr : in  STD_LOGIC_VECTOR (7 downto 0);
                          we_tspsr : in STD_LOGIC;
           oe_tspsr : in  STD_LOGIC_VECTOR (W-1 downto 0);
                          oe_tspsr_row : in STD_LOGIC;
           sclear_tspsr : in  STD_LOGIC;
                          data_out_tspsr : out  TSPSR_SR_DATA_BUS
                          );
end TSP_ShiftRegister;

architecture Behavioral of TSP_ShiftRegister is


component SR_CELL is
                port(
                        d : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
                        clk : IN STD_LOGIC;
                        sclr : IN STD_LOGIC;
                        q : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
                );
        end component;

        SIGNAL INTERNAL_BUS : TSPSR_SR_DATA_BUS;
        signal internal_clock : std_logic;

begin

        ShiftRegisterFirstCell : SR_CELL
                port map(
                        clk=>internal_clock,
                        d=>data_in_tspsr,
                        q=>INTERNAL_BUS(0),
                        sclr=>sclear_tspsr
                );
        
        ShiftRegisterInternal : for i in 1 to W-1 generate
                comp: SR_CELL
                port map(
                        clk=>internal_clock,
                        d=>INTERNAL_BUS(i-1),
                        q=>INTERNAL_BUS(i),
                        sclr=>sclear_tspsr
                );
        end generate ShiftRegisterInternal;
			
			internal_clock<=clk_tspsr and we_tspsr;
        processo:process(clk_tspsr)
                
        variable DATA_OUT: TSPSR_SR_DATA_BUS;
                begin
                        if (clk_tspsr'event and clk_tspsr='1') then
--                                if(we_tspsr='1')then
--                                        internal_clock<=clk_tspsr;
--                                else
--                                        internal_clock<='0';
--                                end if;
                                
                                for i in 0 to W-1 loop
                                        if(oe_tspsr_row='1' and oe_tspsr(i)='1')then
                                                DATA_OUT(i):=INTERNAL_BUS(i);
                                        else
                                                DATA_OUT(i):= (others=>'Z');
                                        end if;
                                end loop;       
                                data_out_tspsr<=DATA_OUT;
                        end if;
                        
--                        if (clk_false_tspsr'event and clk_false_tspsr='1') then
--                                --if(we_tspsr='1')then
--                                        internal_clock<='0';            
--                                --end if;
--                        end if;
                        
                end process;

end Behavioral;